A synchronous shift register uses flip-flops with a clock-to-output propagation delay…

PHYSICS · Multi-part · Fermi University Physics · Electronics, Instrumentation & Communication · Digital electronics, embedded systems and data acquisition · Digital electronics, embedded systems and data acquisition

Electronics for Measurement, Ch Digital logic and its physical realisation

Problem

A synchronous shift register uses

74\mathrm{HC}

flip-flops with a clock-to-output propagation delay

t_{pd,\rm ff} = 17\,\mathrm{ns}

(typical), feeds its output through combinational logic with a worst-case delay

t_{pd,\rm logic} = 40\,\mathrm{ns}

, and the next flip-flop requires a set-up time

t_{\rm su} = 15\,\mathrm{ns}

(a minimum requirement). The clock distribution introduces a skew of

t_{\rm skew} = 3\,\mathrm{ns}

between the clock edges seen by the two flip-flops. ((a)) Write down the timing budget for one clock period and compute the minimum clock period. ((b)) State the corresponding maximum clock frequency.

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