A colleague, defending a design that feeds an unsynchronised sensor edge straight…

PHYSICS · Multi-part · Fermi University Physics · Electronics, Instrumentation & Communication · Digital electronics, embedded systems and data acquisition · Digital electronics, embedded systems and data acquisition

Electronics for Measurement, Ch Digital logic and its physical realisation

Problem

A colleague, defending a design that feeds an unsynchronised sensor edge straight into a state machine's clock-triggered input, argues: "Boolean algebra only recognises two values,

0

and

1

. A CMOS flip-flop has enormous gain right at its switching threshold (an unbuffered inverter's gain magnitude exceeds

20

near mid-supply). An input that lands exactly on the threshold is therefore forced to one value or the other almost immediately, so a fast, high-gain flip-flop can never be caught mid-way: metastability only afflicts badly designed, slow logic." Once the flip-flop's output enters the marginal (in-between) state, it decays away from the threshold with a resolution time constant

\tau = 2.5\,\mathrm{ns}

. ((a)) Explain what is wrong with the claim, in particular what "metastable" means for a circuit whose Boolean model recognises only two values. ((b)) The original design allows only

t_1 = 15\,\mathrm{ns}

from the clock edge to the moment the output is used elsewhere in the circuit. A revised design, adding one synchroniser stage, allows

t_2 = 65\,\mathrm{ns}

. Using

\tau

, estimate the factor by which the probability of the output still being unresolved (and so of a metastability-induced failure) falls between the two designs.

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