A synchronous 4-bit up-counter built from flip-flops occasionally reports a wrong count

PHYSICS · Multi-part · Fermi University Physics · Electronics, Instrumentation & Communication · Digital electronics, embedded systems and data acquisition · Digital electronics, embedded systems and data acquisition

Electronics for Measurement, Ch Digital logic and its physical realisation

Problem

A synchronous 4-bit up-counter built from

74\mathrm{HC}74

flip-flops occasionally reports a wrong count. The fault appears at every clock frequency tried, from

20\,\mathrm{MHz}

down to

1\,\mathrm{kHz}

; slowing the clock does not help. Datasheet figures for the flip-flops (at

4.5\,\mathrm{V}

25^{\circ}\mathrm{C}

): minimum clock-to-output delay

t_{pd,\min} = 4\,\mathrm{ns}

, hold time

t_h = 3\,\mathrm{ns}

(a requirement, not a typical). Two of the flip-flops are clocked from the same source through printed-circuit tracks of very different length, giving a clock skew of

t_{\rm skew} = 6\,\mathrm{ns}

between them. ((a)) A technician says: "the fault must be a set-up time problem, and set-up problems always go away if the clock is slowed down enough; since slowing the clock did not help, the flip-flops must be defective." Find the error in this reasoning. ((b)) Check, using the numbers given, whether the circuit in fact has a hold violation, and state the margin by which the condition is met or failed.

Browse the problem library