A synchronous 3-bit counter is designed to count and then return to (a modulo-6 counter)

PHYSICS · Multi-part · Fermi University Physics · Electronics, Instrumentation & Communication · Digital electronics, embedded systems and data acquisition · Digital electronics, embedded systems and data acquisition

Electronics for Measurement, Ch Digital logic and its physical realisation

Problem

A synchronous 3-bit counter is designed to count

0,1,2,3,4,5

and then return to

0

(a modulo-6 counter), advancing by one on each rising clock edge, starting from the reset state

Q_2Q_1Q_0 = 000

. The clock runs at

f_{\rm clk} = 1\,\mathrm{MHz}

. ((a)) Write, in order, the decimal value of

Q_2Q_1Q_0

after each of the first eight rising clock edges (i.e. the state after edge 1, after edge 2, ..., after edge 8). ((b)) State the period of the waveform on

Q_2

(the most significant bit) in seconds, and say why it is not simply

T_{\rm clk}

multiplied by a power of two, as the period of each bit of an ordinary binary counter is.

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