A superconducting processor's sourced figures (isolated unless stated) are:…
PHYSICS · Multi-part · Fermi University Physics · Quantum Information & Technology · Physical realizations and quantum technologies · Physical realizations and quantum technologies
Quantum Information and Technology, Ch Superconducting qubits and circuit QED
Problem
A superconducting processor's sourced figures (isolated unless stated) are: relaxation time T1=120μs; average two-qubit gate time 35.0ns; average two-qubit gate error r2=5.0×10−3 measured in isolation and 8.0×10−3 measured with all qubits operating; a distance-7 surface code demonstrated on a 105-qubit chip with a 1.1μs cycle.
((a)) Compute how many two-qubit gate times fit within T1, and say whether the DiVincenzo criterion "a relevant decoherence time much longer than the gate operation time" is satisfied.
((b)) The surface code needs a physical error per relevant operation below its threshold, taken here as 1.0%. Using the two-qubit error measured with all qubits operating (the relevant figure for a running device), state whether this platform is below that threshold, and by what factor.
((c)) In one or two sentences, score the DiVincenzo criterion "a scalable physical system" for this platform, citing the 105-qubit chip and naming one factor besides qubit count that must also scale.