A silicon-wafer cooling simulation evolves a binary64 temperature field on a grid for…
PHYSICS · Multi-part · Fermi University Physics · Computational Physics · High-performance and data-driven computational physics · High-performance and data-driven computational physics
Scientific Computing for Physicists, Ch Graphics processors: kernels, memory and the roofline
Problem
A silicon-wafer cooling simulation evolves a binary64 temperature field on a 3072×3072 grid for n=5000 steps with the explicit diffusion scheme. A reference array-expression implementation moves 152B per cell update (Chapter 1's count for the naive array form); a fused two-buffer kernel moves the perfect-reuse minimum of 16B per cell update. The CPU node's measured triad bandwidth is 180GBs−1 and a GPU's measured triad bandwidth is 1400GBs−1.
((a)) Verification: state the tolerance to use when comparing the fused kernel's output against the array expression's after n steps, using the accumulated-rounding-bound form (each step contributing at most ϵmach/2 relative rounding error, ϵmach=2−52 for binary64), and evaluate it.
((b)) By what factor should the fused kernel be faster than the array expression on the same CPU node, from the byte counts alone?
((c)) Predict the GPU fused kernel's speed-up over the CPU fused kernel, from the bandwidth ratio.
((d)) Predict the GPU fused kernel's time per step and its total time for the 5000-step run.
((e)) The wafer's steady pattern is checked against a 2048×2048 complex128 two-dimensional Fourier transform of the field, computed via a GPU array library. A resident-on-device call takes 2.1ms. The host-device bus has peak bandwidth 32GBs−1. By what factor does adding one round-trip transfer of the field increase the FFT's wall time compared with the resident call alone?