A Turing-pattern simulation evolves two coupled binary64 fields (an activator and an…

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Scientific Computing for Physicists, Ch Graphics processors: kernels, memory and the roofline

Problem

A Turing-pattern simulation evolves two coupled binary64 fields (an activator

u

and an inhibitor

v

) with the explicit diffusion scheme on a

5120\times5120

grid, using two buffers per field so that each step moves the perfect-reuse minimum of

16\,\mathrm{B}

per cell for each field,

32\,\mathrm{B}

per cell in total. Both fields are ported to an A100 GPU with data-sheet peak device bandwidth

1555\,\mathrm{GB\,s^{-1}}

, connected to the host by a PCIe 4.0 bus with peak bandwidth

32\,\mathrm{GB\,s^{-1}}

. Every

k

steps both fields are copied to the host and back for a checkpoint of the pattern; between round trips both fields stay resident on the device. ((a)) Write the fraction of the total wall time spent on this round-trip transfer as a function of

k

, defining every symbol used. ((b)) Evaluate the round-trip transfer time and the one-step device time for this run. ((c)) Find the least integer

k

for which the transfer's share of the wall time falls below

2\%

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