Capacitors in Series and Parallel

Open any camera flash, power supply, or audio crossover and you will not find one capacitor — you will find a population. Designers combine capacitors the way you combine LEGO: a bank of electrolytics side by side to bulk up storage, a stack of cells one after another to survive a voltage that would puncture any single one. The question this article answers is deceptively simple: when several capacitors are wired together, what single capacitance does the battery think it sees? The two answers — add the capacitances in parallel, add the reciprocals in series — are easy to memorize and easier to mix up (they are the reverse of the resistor rules you may half-remember from school). So we will not memorize them; we will derive them from the two facts you already own: conductors at a common potential are one equipotential, and charge on an isolated conductor is conserved. The series rule in particular hides a beautiful argument — the floating island of metal between two series capacitors cannot acquire net charge, and that single observation forces every capacitor in the chain to carry identical QQ. Mastering the reduction game buys you real circuits: you will chop a network of five capacitors to one, predict every plate's charge and voltage, and know when the game is unwinnable (the bridge circuit — a preview of Kirchhoff's rules). And one worked example ends on a cliffhanger: connect a charged capacitor to an empty one and a third of the energy simply vanishes. Where it goes is the next article's opening act.

Key takeaways
  • Parallel (same voltage across each): charges add, so Ceq=C1+C2+⋯C_{\mathrm{eq}} = C_1+C_2+\cdots — capacitance in parallel grows.
  • Series (same charge on each): voltages add, so 1Ceq=1C1+1C2+⋯\dfrac{1}{C_{\mathrm{eq}}} = \dfrac{1}{C_1}+\dfrac{1}{C_2}+\cdots — capacitance in series shrinks, below the smallest member.
  • Why series capacitors share one QQ: the conductor island between them is isolated, starts neutral, and stays neutral — its ±\pm charges are induced in equal measure.
  • In series, voltage divides inversely with capacitance: the smallest capacitor eats the biggest voltage — the standard failure mode of careless stacks.
  • NN equal capacitors: NCNC in parallel, C/NC/N in series. Two in series: Ceq=C1C2C1+C2C_{\mathrm{eq}} = \dfrac{C_1C_2}{C_1+C_2} (product over sum).
  • KEY IDEA: every capacitor network reduction is just bookkeeping with two invariants — parallel plates share V, series plates share Q — and when neither invariant applies (the bridge), you have graduated to Kirchhoff's rules.
The core insight

Capacitors in parallel add (Ceq=∑CiC_{\mathrm{eq}}=\sum C_i, shared VV); capacitors in series add reciprocally (1/Ceq=∑1/Ci1/C_{\mathrm{eq}}=\sum 1/C_i, shared QQ — forced by charge conservation on the isolated conductor between them).

Where this lives today

The parallel rule is why bulk energy storage looks the way it does: a grid-scale supercapacitor cabinet or the DC-link of an EV inverter is thousands of cells in parallel banks — capacitances simply adding — with series stacking used only as far as the voltage demands, because every series step divides capacitance and invites balancing headaches. Designers speak of "NNsMMp" configurations (N in series, M in parallel); the arithmetic of this article is the entire content of that notation. The subtler modern presence is unwanted parallelism. Every trace on a printed-circuit board runs in parallel with its neighbours and the ground plane; every node in a chip adds femtofarads of stray capacitance in parallel with whatever the designer intended. Since parallel capacitance adds, strays never cancel — they accumulate, slowing logic transitions and setting the RC limits that the timing chapter will quantify. Circuit simulators like SPICE spend much of their effort solving exactly the node-charge bookkeeping you did by hand in the mixed-network derivation, just with 10910^9 islands.

The physical picture

Both rules become obvious the moment you stop looking at circuit symbols and look at plates.

Parallel wiring joins top plate to top plate and bottom to bottom. Electrically, the two top plates fuse into one big equipotential conductor, and likewise the bottoms: you have built a single capacitor whose plate area is the sum of the areas. Bigger area, proportionally bigger capacitance — from the previous article, C=ε0A/dC=\varepsilon_0A/d wears its area dependence on its sleeve. So parallel capacitance adds, and the container picture says the same thing: two vessels side by side, filled to the same level VV, hold the sum of their contents.

Series wiring chains the capacitors so that the bottom plate of one connects only to the top plate of the next. That connecting piece — plate, wire, plate — touches nothing else: it is an isolated island of conductor. It began life neutral, and no external charge can reach it, so it must remain neutral forever: whatever −Q-Q gets pulled onto its upper face is exactly balanced by +Q+Q pushed onto its lower face. March down the chain and this bookkeeping forces every capacitor to hold the same charge QQ, while their voltages stack up. Same charge, summed voltages, and each Vi=Q/CiV_i=Q/C_i: small capacitors contribute big voltage shares. The chain as a whole stores less per volt than any single link — you have effectively widened the gap.

Figure
Parallel fuses plate areas; series chains isolated islands that share one Q
The two invariants: shared V (parallel) vs shared Q (series) PARALLEL — one big capacitor + − +Q₁ −Q₁ C₁ +Q₂ −Q₂ C₂ same V across both · charges add C_eq = C₁ + C₂ (areas fuse: capacitance grows) SERIES — a chain sharing one Q + +Q −Q +Q isolated island: net 0 −Q − C₁ C₂ same Q on both · voltages add 1/C_eq = 1/C₁ + 1/C₂ (gaps stack: capacitance shrinks below the smallest)

Keep one asymmetry in mind before the algebra: parallel is democratic in charge (each takes Qi=CiVQ_i = C_iV, big capacitors take more) while series is democratic in charge but regressive in voltage (each takes Vi=Q/CiV_i=Q/C_i, small capacitors suffer more). Half the blown capacitor banks in history trace to forgetting the second clause.

The rules, derived

For a network with two terminals, the equivalent capacitance is defined operationally: Ceq=Q/VC_{\mathrm{eq}} = Q/V, where QQ is the charge that flows in through one terminal when voltage VV is imposed across the pair. The network earns the right to be called a single capacitor because the linearity theorem of the previous article applies to any conductor system: Q∝VQ\propto V always, whatever the internal plumbing.

Derivation AParallel Combination: Shared Voltage, Summed Charge

We derive CeqC_{\mathrm{eq}} for capacitors C1,C2,…,CNC_1, C_2, \ldots, C_N wired in parallel across a source at voltage VV. The strategy is to invoke the equipotential property of ideal wires — every top plate sits at the same potential, every bottom plate at the same lower potential — and then simply count the total charge the source must deliver. The only care needed: "parallel" is defined by this shared-voltage topology, not by how the schematic happens to be drawn.

Step 1. All top plates are joined by ideal wire, so they form one equipotential at V+V_+; likewise all bottom plates at V−V_-. Every capacitor therefore sees the identical voltage

V=V+−V−.V = V_+ - V_-.

Why can we treat the wire as one conductor? In equilibrium a conductor is an equipotential (no field inside); an ideal wire extends that equipotential across the circuit. This is the same fact that made each plate an equipotential in the first place.

Step 2. Each capacitor obeys its own definition: Qi=CiVQ_i = C_i V. Big capacitors drink more charge at the common voltage.

Step 3. The source cannot tell the capacitors apart; it only sees the total charge it delivered to the top rail:

Qtot=∑i=1NQi=(∑i=1NCi)V.Q_{\mathrm{tot}} = \sum_{i=1}^{N} Q_i = \Big(\sum_{i=1}^{N} C_i\Big)V.

Step 4. By the operational definition Ceq=Qtot/VC_{\mathrm{eq}} = Q_{\mathrm{tot}}/V,

Ceq=C1+C2+⋯+CNC_{\mathrm{eq}} = C_1 + C_2 + \cdots + C_N

where: the sum runs over every branch between the same two nodes. Physically this is area addition: parallel plates at the same gap fuse into one wide capacitor. Special cases worth caching: NN equal capacitors give NCNC, and adding any capacitor in parallel always increases CeqC_{\mathrm{eq}}. Verified: 2 μF∥3 μF2\ \mu\mathrm{F} \parallel 3\ \mu\mathrm{F} at V=10 VV=10\ \mathrm{V}: Q1=20 μCQ_1=20\ \mu\mathrm{C}, Q2=30 μCQ_2=30\ \mu\mathrm{C}, total 50 μC50\ \mu\mathrm{C} — exactly (5 μF)(10 V)(5\ \mu\mathrm{F})(10\ \mathrm{V}).

Go deeper · Derivation B · 2 minSeries Combination: the Isolated Island Forces One Q
Derivation BSeries Combination: the Isolated Island Forces One Q

Now the chain: C1,C2,…,CNC_1, C_2, \ldots, C_N in series across voltage VV. The heart of the derivation — and the part worth owning for life — is why every capacitor carries the same charge. It is not an assumption about currents; it is charge conservation applied to the stranded conductor between neighbours. We make that argument first, then the formula falls out in two lines. Watch also for what the argument assumes: the island must start neutral, and no sneak paths (leakage, a finger) may touch it.

Step 1. Consider the conductor island between C1C_1 and C2C_2: lower plate of C1C_1 + wire + upper plate of C2C_2. It is completely surrounded by insulation — gap above, gap below, air around. Its net charge is therefore an invariant, and it started at zero:

Qisland=0always.Q_{\mathrm{island}} = 0 \quad\text{always.}

Step 2. Let the source push charge +Q+Q onto the top plate of C1C_1. That charge attracts −Q-Q onto the island's upper face (the facing plate). Neutrality of the island then forces +Q+Q to appear on its lower face — which is the top plate of C2C_2. The island polarizes; it never charges. Why must the induced charges be exactly ∓Q and not something smaller? Because the plates of each capacitor face each other across a narrow gap: every field line from the +Q+Q plate terminates on the facing plate (fringing aside), which pins the facing charge at exactly −Q-Q. The island's neutrality then fixes its other face at +Q+Q. Induction cascades undiminished down the chain.

Step 3. By induction along the chain, every capacitor holds the same QQ:

Q1=Q2=⋯=QN=Q.Q_1 = Q_2 = \cdots = Q_N = Q.

Step 4. Voltages add along the chain (potential is single-valued, and we cross the gaps one after another):

V=∑i=1NVi=∑i=1NQCi=Q∑i=1N1Ci.V = \sum_{i=1}^{N} V_i = \sum_{i=1}^{N} \frac{Q}{C_i} = Q\sum_{i=1}^{N}\frac{1}{C_i}.

Step 5. The operational definition Ceq=Q/VC_{\mathrm{eq}} = Q/V delivers

1Ceq=1C1+1C2+⋯+1CN\frac{1}{C_{\mathrm{eq}}} = \frac{1}{C_1} + \frac{1}{C_2} + \cdots + \frac{1}{C_N}

where: reciprocals add, so CeqC_{\mathrm{eq}} is smaller than the smallest member — series stacking is gap-stacking. For two capacitors the memorable form is Ceq=C1C2C1+C2C_{\mathrm{eq}} = \dfrac{C_1C_2}{C_1+C_2} (product over sum); for NN equal capacitors, C/NC/N. And the voltage division rule falls out of Step 4: Vi=Q/CiV_i = Q/C_i, i.e.

Vi  =  V 1/Ci∑j1/Cj,V_i \;=\; V\,\frac{1/C_i}{\sum_j 1/C_j},

where: the smallest capacitance takes the largest voltage share — the series stack's safety-critical fine print. Verified: 2 μF2\ \mu\mathrm{F} and 3 μF3\ \mu\mathrm{F} in series: Ceq=6/5=1.2 μFC_{\mathrm{eq}} = 6/5 = 1.2\ \mu\mathrm{F}, below the smaller member. At V=10 VV=10\ \mathrm{V}: Q=12 μCQ=12\ \mu\mathrm{C} on each, V1=6 VV_1=6\ \mathrm{V}, V2=4 VV_2=4\ \mathrm{V} — summing to 10 V, with the smaller capacitor carrying the larger voltage.

Figure
Inside-out reduction: collapse the parallel pair, then the series pair, then unwind
Reduce inward, then unwind the invariants outward C₁ = 6 µF 3 µF 1 µF 12 V across the whole chain parallel 6 µF C₂₃ = 4 µF 3 + 1 = 4 µF series C_eq = 2.4 µF 6·4/(6+4) = 2.4 µF Q = 28.8 µC unwind: series hands 28.8 µC to each stage — parallel hands 7.2 V to each branch
Go deeper · Derivation C · 1 minReducing a Mixed Network — and Knowing When You Cannot
Derivation CReducing a Mixed Network — and Knowing When You Cannot

The rules earn their keep on mixed networks. We reduce a standard three-capacitor circuit end to end — C1=6 μFC_1 = 6\ \mu\mathrm{F} in series with the parallel pair C2=3 μFC_2 = 3\ \mu\mathrm{F}, C3=1 μFC_3 = 1\ \mu\mathrm{F}, all across a 12 V12\ \mathrm{V} battery — solving for every charge and voltage, then confront the network the rules cannot touch. The strategy is always inside-out: find a pure-parallel or pure-series cluster, collapse it, redraw, repeat; then unwind, carrying the invariants (shared VV backward through parallel, shared QQ backward through series) to recover the internal state.

Step 1. Collapse the parallel pair: C23=C2+C3=3+1=4 μFC_{23} = C_2 + C_3 = 3+1 = 4\ \mu\mathrm{F}.

Step 2. Collapse the resulting series pair: Ceq=C1C23C1+C23=6×410=2.4 μFC_{\mathrm{eq}} = \dfrac{C_1C_{23}}{C_1+C_{23}} = \dfrac{6\times4}{10} = 2.4\ \mu\mathrm{F}.

Step 3. Total charge drawn from the battery: Q=CeqV=(2.4 μF)(12 V)=28.8 μCQ = C_{\mathrm{eq}}V = (2.4\ \mu\mathrm{F})(12\ \mathrm{V}) = 28.8\ \mu\mathrm{C}.

Step 4. Unwind the series step: series members share QQ, so C1C_1 and the cluster each hold 28.8 μC28.8\ \mu\mathrm{C}. Their voltages: V1=Q/C1=4.8 VV_1 = Q/C_1 = 4.8\ \mathrm{V} and V23=Q/C23=7.2 VV_{23} = Q/C_{23} = 7.2\ \mathrm{V}. Check: 4.8+7.2=124.8+7.2 = 12 ✓.

Step 5. Unwind the parallel step: parallel members share V23=7.2 VV_{23}=7.2\ \mathrm{V}, so Q2=C2V23=21.6 μCQ_2 = C_2V_{23} = 21.6\ \mu\mathrm{C} and Q3=C3V23=7.2 μCQ_3 = C_3V_{23} = 7.2\ \mu\mathrm{C}. Check: Q2+Q3=28.8 μC=QQ_2+Q_3 = 28.8\ \mu\mathrm{C} = Q ✓ — the island between C1C_1 and the pair polarized into −28.8 μC-28.8\ \mu\mathrm{C} facing C1C_1 and +28.8 μC+28.8\ \mu\mathrm{C} split across the pair. Why do both checks matter? Each one audits an invariant (loop voltage, island charge). In an exam or a design review, a reduction that fails either check is wrong somewhere upstream — the checks are free and catch nearly everything.

Step 6. Now the confession. Take five capacitors in a bridge: C1,C2C_1, C_2 from the top terminal to nodes a,ba, b; C3,C4C_3, C_4 from a,ba, b to the bottom terminal; C5C_5 across aa–bb. Unless the bridge is balanced (C1C4=C2C3C_1C_4 = C_2C_3, making C5C_5 idle), no two of these are in series (the nodes a,ba, b have three connections, so no isolated two-plate island exists) and none are in parallel (no two share both nodes). The reduction game is unwinnable: you must write node-charge conservation and loop-voltage equations directly — the systematic method that Kirchhoff's Rules builds for exactly this moment. Verified: all numbers above recomputed independently — 28.8/6=4.828.8/6 = 4.8, 28.8/4=7.228.8/4 = 7.2, 3×7.2=21.63\times7.2 = 21.6, 1×7.2=7.21\times7.2 = 7.2, and 21.6+7.2=28.821.6+7.2 = 28.8.

Limiting cases

caseresultmeaning
NN equal CC in parallelNCNCarea addition; storage scales with the bank
NN equal CC in seriesC/NC/Ngap addition; voltage rating scales with the stack
series with one huge member C1→∞C_1\to\inftyCeq→C_{\mathrm{eq}}\to (rest of chain)a big-enough series capacitor is invisible — it is just wire with a pause
series with one tiny member C1→0C_1\to0Ceq→C1C_{\mathrm{eq}}\to C_1the smallest link dominates and takes essentially all the voltage
parallel with one tiny memberCeqC_{\mathrm{eq}} barely movessmall parallel additions are perturbations — but this is exactly how stray capacitance sneaks into every real node
balanced bridge C1C4=C2C3C_1C_4=C_2C_3C5C_5 carries no chargesymmetry makes Va=VbV_a=V_b; the unwinnable network becomes winnable

Pitfall

Worked examples

Example 1 — a supercapacitor stack (confidence builder). A backup supply needs to ride on a 12 V rail, but supercapacitor cells are rated only 2.7 V. Five cells of C=100 FC = 100\ \mathrm{F} each are wired in series. What is the stack's capacitance, the voltage per cell at 12 V, and the total charge shuttled?

Step 1. Series, equal members: Ceq=C/N=100/5=20 FC_{\mathrm{eq}} = C/N = 100/5 = \boxed{20\ \mathrm{F}}.

Step 2. Equal capacitances split VV equally (the one case where they do): Vcell=12/5=2.4 VV_{\mathrm{cell}} = 12/5 = 2.4\ \mathrm{V} — safely under the 2.7 V rating, which is the entire reason for the stack.

Step 3. Charge: Q=CeqV=20×12=240 CQ = C_{\mathrm{eq}}V = 20\times12 = \boxed{240\ \mathrm{C}} — the same 240 C resides on every cell (shared-QQ invariant), each at 2.4 V. Note what was traded: five 100 F cells bought a 20 F system; series stacking spends capacitance to buy voltage headroom.

Example 2 — charge redistribution, ending on a cliffhanger (exam level). A C1=4 μFC_1 = 4\ \mu\mathrm{F} capacitor is charged to V0=12 VV_0 = 12\ \mathrm{V}, disconnected from the battery, then connected plus-to-plus and minus-to-minus across an uncharged C2=8 μFC_2 = 8\ \mu\mathrm{F}. Find the final voltage, the final charges, and audit the energy.

Step 1. Initial state: Q0=C1V0=48 μCQ_0 = C_1V_0 = 48\ \mu\mathrm{C}; no source remains attached, so total charge on the joined top plates is conserved.

Step 2. After connection the two capacitors are in parallel (both plate pairs joined): one equipotential, shared VfV_f, combined capacitance C1+C2=12 μFC_1+C_2 = 12\ \mu\mathrm{F}. Charge conservation:

Vf=Q0C1+C2=48 μC12 μF=4 V.V_f = \frac{Q_0}{C_1+C_2} = \frac{48\ \mu\mathrm{C}}{12\ \mu\mathrm{F}} = \boxed{4\ \mathrm{V}}.

Step 3. Final charges: Q1=C1Vf=16 μCQ_1 = C_1V_f = 16\ \mu\mathrm{C}, Q2=C2Vf=32 μCQ_2 = C_2V_f = 32\ \mu\mathrm{C}. Check: 16+32=48 μC16+32 = 48\ \mu\mathrm{C} ✓.

Step 4. Energy audit, using U=12QVU = \tfrac12 QV (from Work and Energy of a Charge Configuration; the systematic ledger is the next article's job). Before: Ui=12(48 μC)(12 V)=288 μJU_i = \tfrac12(48\ \mu\mathrm{C})(12\ \mathrm{V}) = 288\ \mu\mathrm{J}. After: Uf=12(48 μC)(4 V)=96 μJU_f = \tfrac12(48\ \mu\mathrm{C})(4\ \mathrm{V}) = 96\ \mu\mathrm{J}.

Step 5. Two-thirds of the energy — 192 μJ192\ \mu\mathrm{J} — is gone, and nothing in this article can tell you where. Charge is perfectly conserved; energy is not. No resistor was specified, yet the loss is real, and (stranger still) its fraction, C2/(C1+C2)=2/3C_2/(C_1+C_2) = 2/3, is fixed by the capacitances alone. The resolution — and the reason the answer does not depend on how lossy the connecting wire is — opens Capacitor Energy and Dielectrics.

History

Origins · 1 minJames Clerk Maxwell and how this was discovered
JC
James Clerk Maxwell
1831–1879 · Edinburgh and Cambridge

Maxwell appears in this chapter not for fields but for bookkeeping: he is the physicist who turned "capacitance" from a property of one gadget into the linear algebra of many. In the Treatise on Electricity and Magnetism (1873) he set up the general problem — nn conductors, arbitrary shapes — and showed the charges and potentials are linked by a symmetric matrix of coefficients: coefficients of capacity on the diagonal, coefficients of induction off it. Series and parallel formulas are the two easiest corollaries; the bridge network that defeats them is, in Maxwell's frame, just a matrix that refuses to factor. The symmetry of that matrix (his reciprocity relations) is a genuine theorem with real consequences — measure how conductor 1 influences 2 and you know how 2 influences 1. Fittingly, the man who systematized capacitance spent his last years editing the papers of Henry Cavendish, discovering that the recluse had measured half of these coefficients a century before anyone defined them.

History
1746
— Daniel Gralath in Danzig wires Leyden jars into the first "battery" of capacitors in parallel, seeking (successfully) a bigger shock
1749
— Benjamin Franklin describes his linked "electrical battery" of jars, borrowing the artillery word that would stick to every charge-storage array since
1773
— Cavendish, comparing "batteries" of jars against single jars, quietly verifies capacity addition in his unpublished notebooks
1873
— Maxwell's Treatise recasts multi-conductor electrostatics as the matrix of coefficients of capacity and induction
1940
s — Voltage-graded series capacitor stacks become standard in radar modulators and X-ray supplies, institutionalizing the balancing problem

Going further

References. Halliday, Resnick & Walker, Fundamentals of Physics, ch. 25 (combinations, worked networks); Purcell & Morin, Electricity and Magnetism, §3.5–3.7 (coefficients of capacitance, systems of conductors); Maxwell, A Treatise on Electricity and Magnetism (1873), vol. I, ch. III (the general theory this article's rules specialize).

Provenance. Authored fresh for the SuperSTEM E&M track's circuits chapter (recon-§d gap heal); sources: v3 circuit pilots (rewritten to UG register) + legacy wiki circuit articles (narrative) — no AllQFT base exists for this topic.

Prerequisites. Capacitance.

Leads to. Capacitor Energy and Dielectrics · Kirchhoff's Rules · RC Circuits.

How do I tell series from parallel in a messy schematic?

Ignore the drawing and interrogate the nodes. Two elements are in parallel if and only if both their terminals connect to the same two nodes (they share voltage no matter what). They are in series if and only if they share one node to which nothing else connects (that node is the isolated island, so they share charge/current). If neither test passes for any pair — as in the bridge — the network is irreducible by these rules and you need the systematic method of Kirchhoff's rules.

Why are the capacitor rules the opposite of the resistor rules?

Because CC sits in the denominator of its voltage law. A capacitor obeys V=Q/CV = Q/C while a resistor obeys V=IRV = IR: in series the shared quantity (QQ or II) rides through, and voltages add — which sums 1/C1/C for capacitors but RR for resistors. If you work instead with the elastance S=1/CS = 1/C (a real if old-fashioned quantity), capacitors behave exactly like resistors: elastances add in series. The "opposite" rules are one rule applied to reciprocal variables.

Does the island between series capacitors really stay perfectly neutral?

As long as it is truly isolated, yes — charge conservation is not approximate. In practice three things can violate the assumption: leakage through imperfect dielectrics or humid air (giving the island a slow path to charge), a deliberately attached balancing network, or an initial condition where the island was charged before assembly. High-voltage engineers deal with the first case daily: over minutes-to-hours, leakage redistributes series-stack voltages from the 1/C1/C division toward a division set by leakage resistances — one more reason real stacks carry balancing resistors that make the redistribution deliberate and safe.

If series stacking lowers the capacitance, why would anyone ever do it?

Voltage. Each capacitor in the chain absorbs only its share of the total, so a stack of NN matched cells survives NN times the single-cell rating at the cost of C/NC/N capacitance. When the energy 12CV2\tfrac12CV^2 is the metric, the trade is neutral for ideal matched cells (C/NC/N at voltage NVNV stores N×N\times the single-cell energy — exactly what NN cells should hold). Series stacking spends no energy capacity; it repackages it at higher voltage, which is what power electronics usually wants.

In the redistribution example, could I avoid the energy loss by connecting the capacitors more carefully?

Not within circuit theory's rules. The final state is fixed by charge conservation alone, so the initial and final energies — and hence the deficit — are decided before you choose wires. Making the connection resistance smaller does not save energy; it only makes the loss happen faster (and shifts some of it from heat to radiation). The loophole is to change the process: insert an inductor and you can swing the charge across resonantly, catching it at the right moment (the LC chapter shows the mechanism), which is how real "charge-recycling" power circuits dodge the two-capacitor tax.

What happens if I connect the charged capacitor to the uncharged one plus-to-minus instead?

Then the conserved top-plate charge is Q0′=Q1−Q2Q_0' = Q_1 - Q_2 evaluated with signs — for our numbers, 48 μC48\ \mu\mathrm{C} meeting 00 gives the same magnitude, but if both had been charged, opposing connection cancels charge: two equal capacitors at equal-and-opposite charge annihilate to Vf=0V_f = 0, dumping all the stored energy into the wire. This is not academic: paralleling charged banks with reversed polarity is a classic and violent lab accident. Always meter a bank before connecting.

Do these rules work when a dielectric or a real battery is involved?

The rules themselves survive untouched — they rest only on equipotential wires and charge conservation, so filled capacitors just bring their boosted CC values (κC0\kappa C_0, next article) to the same arithmetic. What changes with a real source is the bookkeeping around the network: a battery holds VV fixed and will move charge (and energy) in or out as you rearrange things, whereas an isolated network holds QQ fixed. Series/parallel reduction is indifferent; energy accounting is emphatically not, and the fixed-QQ versus fixed-VV distinction becomes the organizing principle of the next article.

Before this

Where this leads