SRAM versus DRAM

A memory cell is the smallest circuit that stores one bit. SRAM (Static Random-Access Memory) implements a cell as a pair of cross-coupled inverters — a bistable latch built from six transistors (the "6T cell"). Because the two inverters actively reinforce each other's output, the cell holds its state indefinitely as long as power is supplied; no periodic action is needed to keep the bit from decaying. This is what "static" means: the stored value is stable without intervention.

DRAM (Dynamic Random-Access Memory) implements a cell as one transistor acting as a switch plus one capacitor that stores charge (the "1T1C cell"). A charged capacitor represents a 1, a discharged one a 0. Capacitors are not perfect insulators — leakage current slowly drains the charge — so every DRAM cell must be periodically refreshed: read out and rewritten before the charge decays past the threshold that distinguishes a 1 from a 0. This is what "dynamic" means: the stored value decays and must be dynamically restored. Reading a DRAM cell is also destructive — the act of sensing the tiny charge on the capacitor drains it — so every DRAM read is followed by an automatic rewrite of that row. These two circuit choices propagate into every practical property that matters for computer architecture: cell area, access latency, power consumption, and manufacturing cost per bit. The 6T SRAM cell needs roughly 5–10 times the silicon area of a 1T1C DRAM cell, so for the same chip area DRAM stores far more bits — this is the density advantage. But SRAM's active bistable circuit resolves to a stable logic level almost immediately when accessed, giving access times of roughly 1–3 processor cycles, while DRAM's sense amplifiers must detect a minuscule charge difference on a capacitor connected to a long, capacitive bit line, an operation that takes tens of nanoseconds — the latency disadvantage. The result is a clean, physically grounded division of labor that anchors the entire Memory Hierarchy: put SRAM wherever speed matters most and the data set is small (registers, L1/L2/L3 caches), and put DRAM wherever capacity matters most and some latency is tolerable (main memory).

The SRAM cell (6T)

Two CMOS inverters are cross-coupled: the output of inverter A feeds the input of inverter B, and vice versa. This creates two stable states — (A=0, B=1) and (A=1, B=0) — and no stable in-between state, hence bistable. Two additional access transistors connect the cell's two internal nodes to a pair of complementary bit lines (BL and BL̄), gated by a word line (WL). To read, the word line is raised, the access transistors turn on, and the pre-charged bit lines are pulled apart by the cell's stored value; a sense amplifier detects the small voltage difference and amplifies it to a full logic level. To write, the bit lines are driven hard with the new value and the word line is raised, forcing the cross-coupled inverters to flip if necessary. Because the inverters actively drive their outputs, the read is non-destructive, and no refresh is ever needed.

The DRAM cell (1T1C)

A single access transistor connects a storage capacitor to a bit line, gated by a word line. To write, the word line is raised and the bit line is driven to the desired voltage, charging or discharging the capacitor. To read, the word line is raised and the capacitor's charge redistributes onto the (much larger) bit line capacitance, producing a tiny voltage perturbation that a sense amplifier detects and amplifies — this amplification simultaneously restores the correct full-swing value onto the bit line and back into the cell, which is why a DRAM read is followed by an implicit rewrite. Left untouched, leakage paths (through the access transistor and the capacitor dielectric) drain the charge over milliseconds, so a background refresh operation must read and rewrite every row on a strict schedule, typically once every 64 ms for the whole array.

Refresh, step by step

``` // DRAM background refresh (conceptual) REFRESH_INTERVAL_MS = 64 // JEDEC-typical full-array refresh window NUM_ROWS = rows_in_array function REFRESH_ALL_ROWS(): // Spread refresh work evenly to avoid one giant stall per_row_period = REFRESH_INTERVAL_MS / NUM_ROWS for row in 0 .. NUM_ROWS - 1: wait_until(next_scheduled_time(row, per_row_period)) ACTIVATE(row) // sense amplifiers read the row, restoring charge PRECHARGE(row) // close the row, leaving bit lines ready for next access ``` ``` // Reading one SRAM bit (non-destructive) function SRAM_READ(cell): precharge(BL, BL_bar) // both bit lines pulled to Vdd/2 or Vdd assert(cell.WL = 1) // raise word line delta = sense_amplifier(BL, BL_bar) // amplify the differential swing return delta > 0 ? 1 : 0 // cell's cross-coupled inverters still hold original value: non-destructive ``` ``` // Reading one DRAM bit (destructive, needs rewrite) function DRAM_READ(cell): precharge(BL, Vdd/2) // bit line pre-set to reference voltage assert(cell.WL = 1) // raise word line, connect capacitor to BL delta = sense_amplifier(BL) // tiny charge-sharing perturbation, amplified bit = (delta > 0) ? 1 : 0 drive(BL, bit == 1 ? Vdd : 0) // sense amp restores full-swing value // capacitor is rewritten to bit via BL: this IS the refresh, incidental to read return bit ``` The key structural fact both snippets expose: SRAM's read path never needs to "put the value back," while DRAM's read path must restore the value as an unavoidable side effect of sensing it. This single difference cascades into the timing, area, and power numbers architects rely on.

Treat "complexity" here as physical resource cost rather than algorithmic asymptotic cost, since these are hardware primitives, not algorithms — but the same discipline of honest accounting applies.

Area per bit. An SRAM cell needs six transistors laid out with two cross-coupled inverters and two access transistors, plus the wiring for two bit lines and isolation to keep the bistable pair from being disturbed by neighboring cells. A DRAM cell needs one transistor and one capacitor, and the capacitor can often be built in a "trench" or "stack" structure that uses the vertical dimension of the die rather than more lateral area. Empirically, this yields roughly a 5–10× area advantage for DRAM per bit, which is why DRAM chips reach gigabit-per-die densities that SRAM does not approach at competitive cost.

Latency. SRAM latency is dominated by the propagation delay through the cross-coupled inverters and the sense amplifier resolving a bit line pair that was actively driven by the cell — a few hundred picoseconds to a couple of nanoseconds in modern processes, translating to roughly 1–3 CPU cycles for an L1 cache access. DRAM latency is dominated by (1) activating a row (driving the word line and letting all capacitors in that row share charge onto their bit lines), (2) the sense amplifier resolving a much smaller voltage perturbation against a much larger bit-line capacitance, and (3) precharging the array before the next access. This full activate–sense–precharge cycle costs tens of nanoseconds, an order of magnitude slower than SRAM, before the request even leaves the DRAM chip and crosses the memory bus.

Power. SRAM's cross-coupled inverters draw static leakage current continuously (to hold state) even when idle, scaling with transistor count and process leakage; large SRAM caches are a major source of a chip's static power. DRAM cells draw negligible static power when idle (the capacitor just leaks slowly), but refresh operations add a periodic energy cost, and this cost grows with array size and shrinks as the technology improves retention time — a genuine tradeoff, not a free win for DRAM.

Correctness of refresh. The invariant that must hold is: every DRAM row is refreshed at least once within its guaranteed retention window (the JEDEC-specified interval, canonically 64 ms across the whole array, i.e., an average interval per row of 64 ms ÷ (number of rows)). If any row is skipped past its retention window, some cells may decay far enough that the sense amplifier reads the wrong logic value — silent data corruption. Correctness reduces to a scheduling guarantee: the refresh controller must issue a refresh command to every row within the interval, regardless of concurrent read/write traffic, which is why DRAM controllers interleave refresh commands with normal accesses and why refresh consumes a small but nonzero fraction of memory bandwidth (typically a few percent).

Why the split is efficient, not arbitrary. If a system used only SRAM, main memory would be enormously expensive and would consume far more chip area and static power for the same capacity — infeasible at gigabyte scale. If a system used only DRAM, register files and L1 caches would be an order of magnitude slower, and since Locality of Reference guarantees that a small working set is accessed overwhelmingly often, that slowdown would dominate almost every instruction. Using SRAM for small, hot structures and DRAM for large, cooler main memory is the efficient point on the cost–capacity–latency surface, and it is exactly the physical justification for building a multi-level Memory Hierarchy instead of a flat address space in one technology.

Consider a simplified but realistic system and trace the consequences of the cell-level facts through to system numbers.

Now trace a single memory access request through both technologies to see the latency gap concretely.

Step 1 — CPU issues a load for address `0x1000`.

Step 2 — L1 cache (SRAM) lookup. The cache's tag array and data array are SRAM. The processor asserts a word line for the indexed set, the bit lines swing based on the stored bistable values, and a sense amplifier resolves tag and data within roughly 1 cycle (~0.3–1 ns at multi-GHz clock). Suppose this is a cache miss — the tag doesn't match.

Step 3 — Request falls to DRAM main memory. The memory controller issues:

• `ACTIVATE row R` — the word line for the row is raised, every capacitor in that row shares charge onto its bit line (~15–20 ns).
• Sense amplifiers detect the tiny perturbation and drive it to a full logic level, simultaneously restoring the row's capacitors (~part of the same window).
• `READ column C` — the desired word is selected from the now-open row and driven onto the data bus (~10–15 ns).
• `PRECHARGE` — bit lines are reset for the next access to a different row (~15 ns).

Total: roughly 50–70 ns, versus ~1 ns for the SRAM hit — a 50–70× latency gap, which is exactly why a cache miss is expensive and why the memory hierarchy is designed to make misses rare via Locality of Reference.

Step 4 — Data returns and is placed into the SRAM cache (a new cache line is installed), so that if the same address (or a nearby one, by locality) is requested again soon, Step 2 succeeds and Step 3 is skipped entirely. This is the entire economic argument for caching in one trace: pay the DRAM latency once, then reap many cheap SRAM hits. Meanwhile, in the background, unrelated to this specific access, the DRAM's refresh controller is independently cycling through all rows on its 64 ms schedule:

If the memory controller ever fell behind this schedule — say, due to a burst of competing read/write traffic that starved refresh commands for too long — a row could decay past its safe retention margin, and a subsequent read could return a corrupted bit. This never happens in a correctly designed controller because refresh commands are given guaranteed priority slots, illustrating that DRAM's density advantage is not free: it is purchased with an ongoing scheduling obligation that SRAM never incurs.

The 6T SRAM cell and the 1T1C DRAM cell both emerged from the same era of MOS integrated circuit development, but from different design goals: SRAM prioritized speed and simplicity of control, DRAM prioritized density to make large-scale memory economically viable.

Every general-purpose processor built since the 1970s embodies this split. Register files and L1/L2/L3 caches are built from SRAM because they must respond within a handful of processor cycles, directly enabling the fast tiers assumed by Cache Basics: Blocks, Hits, and Misses — the entire hit/miss framework only makes sense because SRAM caches are fast enough to be worth checking first. Main memory — the DIMMs in a desktop, server, or phone — is built from DRAM (commonly DDR4/DDR5 today) because gigabytes of capacity at an affordable price are only possible with the small 1T1C cell, and this large-but-slower tier is exactly what makes Virtual Memory: Concept and Motivation necessary: software needs an abstraction that lets a program's address space span far more capacity than any single fast tier could hold, backed transparently by this dense, cheaper technology. Beyond general-purpose CPUs, GPUs use large on-chip SRAM structures (register files, shared memory, L2 caches) to feed thousands of parallel execution units with minimal stall, while relying on high-bandwidth DRAM (GDDR, HBM) for the large datasets those units chew through. Embedded systems and microcontrollers often use SRAM exclusively for small, latency-critical working memory when capacity requirements are modest enough that DRAM's refresh circuitry and controller complexity are not worth the cost. Even outside computing, the cell-level tradeoff generalizes: any system needing both speed and capacity in the same design will end up splitting into a small fast tier and a large slow tier, precisely because no single physical mechanism optimizes both simultaneously — the same principle underlying disk caching, content-delivery networks, and multi-level storage in distributed systems.

Ask the tutor: How does DDR (double data rate) timing interact with DRAM's activate–sense–precharge cycle to hide latency?