Reading and Building Quantum Circuit Diagrams

A quantum circuit diagram is a graphical representation of a sequence of unitary operations (and, optionally, measurements) acting on a fixed set of qubits. Formally, it depicts a factorization of a global unitary $U$ acting on an $n$-qubit register into a time-ordered product of layers (also called moments or time steps):

where each $U_t$ is itself a tensor product of gates (and identities on untouched qubits) acting within time step $t$. The diagram convention is that time flows left to right, so $U_1$ is drawn as the leftmost column and $U_T$ as the rightmost — but in the matrix product they compose in the reverse order, since the state $|\psi_{\text{out}}\rangle = U|\psi_{\text{in}}\rangle$ requires $U_1$ to act on $|\psi_{\text{in}}\rangle$ first. Each horizontal wire represents one qubit's world-line through time; it is not a physical wire carrying a bit, but a bookkeeping line tracking which subsystem is being acted on. A box labeled with a gate name (H, X, Z, T, S, $R_\theta$, …) denotes a single-qubit unitary applied at that point in time. A filled circle (•) joined by a vertical line to another symbol denotes a control: the attached operation is applied conditioned on that qubit's basis state (by convention, control on $|1\rangle$ unless marked open, meaning control on $|0\rangle$). A ⊕ (circled plus) on a wire, joined to a control by a vertical line, denotes the target of a CNOT — the standard shorthand for the Pauli-$X$ controlled operation central to Two-Qubit Gates and the CNOT. A meter symbol (a small dial icon) denotes measurement in the computational basis, terminating that wire's quantum evolution and producing a classical bit, often drawn continuing as a thin double line (classical wire) to a later classically-controlled gate. Two structural rules make diagrams compositional rather than an unstructured picture. First, gates drawn in the same vertical column but on disjoint qubits act simultaneously and, since they act on different tensor factors, always commute — so their left-right order within a column is a drawing choice, not a semantic one. Second, gates connected by a vertical line spanning multiple wires represent a single multi-qubit gate (e.g., CNOT, Toffoli, controlled-phase), and such a gate must be read as one indivisible operation on the joint state of the wires it touches, not as two independent single-qubit boxes.

Reading a diagram is the process of converting the picture into an explicit unitary (or a sequence of Kronecker products and matrix multiplications) that you can apply to a state vector. Building a diagram is the reverse: given a target operation, decomposing it into the standard vocabulary of boxes, controls, and targets and laying them out correctly in time.

Step-by-step reading procedure

``` READ-CIRCUIT(diagram, n_qubits): columns ← partition diagram into time-ordered vertical slices, such that no two gates in the same slice overlap on a shared qubit unless they form one multi-qubit gate U ← Identity(2^n_qubits) for t = 1 to len(columns): U_t ← Identity(2^n_qubits) for each gate g acting on qubit-set S in column[t]: U_t ← U_t with the block on S replaced by the matrix of g tensored appropriately with identity on the remaining qubits U ← U_t * U # left-most column applied first,

# so it multiplies state from the right return U ```

Step-by-step building procedure

``` BUILD-CIRCUIT(target_unitary U, n_qubits): decompose U into a product U = U_T ... U_2 U_1 (each U_t expressible as single/two-qubit gates on disjoint or jointly-entangling qubit sets) for t = 1 to T: draw column t left to right: for each single-qubit factor in U_t: draw a labeled box for each controlled operation: draw a filled dot on the control wire(s), connected by a vertical line to the target symbol (⊕ for X, box for other targets) return diagram ``` Two worked constructions make this concrete.

Bell-state circuit. The goal is to map $|00\rangle$ to the maximally entangled state $\frac{1}{\sqrt2}(|00\rangle + |11\rangle)$. Reading the standard textbook diagram: qubit $q_0$ (top wire) has an H box in column 1; column 2 is a CNOT with control on $q_0$ and target ⊕ on $q_1$. Multiplying:

Applied to $|00\rangle$: $H\otimes I$ gives $\frac{1}{\sqrt2}(|00\rangle+|10\rangle)$, then CNOT flips the second qubit whenever the first is $1$, giving $\frac{1}{\sqrt2}(|00\rangle + |11\rangle)$ — the Bell state $|\Phi^+\rangle$.

SWAP circuit. The goal is the unitary that exchanges the states of two qubits, $\text{SWAP}|a\rangle|b\rangle = |b\rangle|a\rangle$. It can be drawn with a compact ⨉—⨉ symbol on two wires connected by a vertical line, or expanded into three CNOTs alternating control/target:

Both diagrams denote the identical $4\times4$ permutation matrix; the three-CNOT version is what you get after decomposing SWAP into the native gate set most hardware actually supports.

Reading this figure column by column: $t{=}1$ applies $H\otimes I \otimes I$; $t{=}2$ applies a Toffoli (CCX) with controls on $q_0,q_1$ and target on $q_2$; $t{=}3$ applies $I\otimes I\otimes S$; $t{=}4$ measures all three qubits. The overall unitary before measurement is

Notice the matrix product order is the reverse of the left-to-right drawing order — this reversal is the single most common source of reading errors.

Correctness of the reading algorithm. The claim that `READ-CIRCUIT` produces the correct global unitary rests on an invariant: after processing columns $1,\dots,t$, the accumulated matrix $U^{(t)} = U_t \cdots U_1$ equals the unitary that the diagram's first $t$ columns implement, when applied to the initial state. This holds by induction. Base case $t=0$: $U^{(0)} = I$, trivially correct (no gates applied yet). Inductive step: assuming $U^{(t-1)}$ is correct, column $t$ acts on the state $U^{(t-1)}|\psi_0\rangle$ by left-multiplication with $U_t$ (well defined because gates within a column act on disjoint qubits or are declared as one joint multi-qubit gate, so $U_t$ is a well-formed tensor product), giving $U^{(t)}|\psi_0\rangle = U_t U^{(t-1)} |\psi_0\rangle$, matching the update rule. By induction the final $U^{(T)}$ is the diagram's unitary. The subtlety that must be handled correctly is within-column commutativity: gates on disjoint qubits commute because they act as $A\otimes I$ and $I\otimes B$ respectively, and $(A\otimes I)(I\otimes B) = A\otimes B = (I\otimes B)(A\otimes I)$. This is why it is legitimate to draw them in one column without specifying a left-right order between them — but it also means a diagram is ambiguous (or wrong) if two gates in the same column act on an overlapping qubit without being declared as a single joint operation.

Complexity of simulating a read circuit. If the circuit has $n$ qubits, $T$ time-columns, and each column's unitary is built explicitly as a $2^n \times 2^n$ matrix, then naive dense simulation costs $O(T \cdot 4^n)$ time and $O(4^n)$ space just to store one layer's matrix, dominated by matrix multiplication and storage of $2^n$-dimensional state vectors — this is why classical simulation of quantum circuits is exponential in qubit count and only tractable for small $n$ (roughly $n \lesssim 30$–$50$ depending on structure and available memory, far below cryptographically or chemically relevant sizes). In practice, simulators exploit gate locality: applying a $k$-qubit gate to a $2^n$-dimensional state vector costs $O(2^n \cdot 2^k)$ rather than $O(4^n)$, since only amplitudes are updated in place rather than building the full matrix — a standard optimization but still exponential overall in $n$.

Cost metrics for diagrams themselves. Three numbers characterize a circuit diagram's resource footprint, and all three are read directly off the picture:

• Width $= n$, the number of horizontal wires — the number of physical qubits required.
• Depth $= T$, the number of time-columns — a lower bound on latency, since columns must execute sequentially.
• Gate count $= \sum_t |\{\text{gates in column } t\}|$ — total operations, relevant for error accumulation on noisy hardware.

Depth and gate count are not the same: a circuit can have many gates packed into few columns (high parallelism, low depth) or the same number of gates spread thinly across many columns (low parallelism, high depth). Because physical decoherence accumulates roughly per unit time, minimizing depth, not just gate count, is often the binding constraint when building a diagram for real hardware — a genuine engineering tradeoff, since depth-optimal decompositions sometimes require more total gates or more ancilla qubits (increasing width) than a depth-naive decomposition.

Honesty about diagram ambiguity. Not every visual convention is universal: some sources draw an open circle for control-on-$|0\rangle$, some use a boxed "X" instead of ⊕ for the CNOT target, and classical-wire (double-line) conventions for measurement-conditioned gates vary between papers and software packages. Fluency means checking a legend, not assuming.

Trace the Bell-state circuit and then a phase-augmented three-gate circuit fully, amplitude by amplitude.

Bell-state trace. Input $|\psi_0\rangle = |00\rangle$, basis order $|q_0 q_1\rangle \in \{00,01,10,11\}$.

Explicitly, $H\otimes I$ applied to $|00\rangle$ gives $\tfrac{1}{\sqrt2}(|0\rangle+|1\rangle)\otimes|0\rangle = \tfrac1{\sqrt2}(|00\rangle+|10\rangle)$. The CNOT matrix (control first qubit) flips the second qubit's bit whenever the first is $1$: term $|00\rangle$ is untouched (control is $0$), term $|10\rangle \mapsto |11\rangle$ (control is $1$, target flips). Result: $\tfrac1{\sqrt2}(|00\rangle+|11\rangle) = |\Phi^+\rangle$, confirmed entangled since it cannot be written as a product state $(\alpha|0\rangle+\beta|1\rangle)\otimes(\gamma|0\rangle+\delta|1\rangle)$ — direct computation shows no such factorization reproduces zero amplitude on $|01\rangle$ and $|10\rangle$ simultaneously with nonzero amplitude on $|00\rangle,|11\rangle$ unless $\alpha\delta=\beta\gamma=0$ contradicting $\alpha,\beta,\gamma,\delta\neq0$.

Three-column trace with a phase gate. Take input $|q_0q_1\rangle = |1\rangle|1\rangle$ (two qubits), and read the diagram: column 1 is CNOT (control $q_0$, target $q_1$); column 2 is an $S$ gate ($S = \text{diag}(1,i)$, a quarter-turn phase gate) on $q_1$ alone.

Here the CNOT maps $|11\rangle \mapsto |10\rangle$ (target flips because control is $1$), and then $S$ acting on $q_1 = |0\rangle$ contributes only the trivial phase $S|0\rangle = |0\rangle$ (recall $S|1\rangle = i|1\rangle$, but that branch is not populated). Rerunning with input $|q_0 q_1\rangle = |01\rangle$ instead: CNOT leaves it unchanged (control is $0$), giving $|01\rangle$; then $S$ on $q_1=|1\rangle$ contributes a phase $i$, giving final state $i\,|01\rangle$ — a global phase invisible to measurement probabilities but essential if this circuit is a sub-block of a larger interfering computation, illustrating why phase gates (central to Phase Gates) must be tracked exactly, not rounded off as "just a phase, ignore it," whenever the circuit is embedded in a larger interference-based algorithm.

The circuit-diagram notation for quantum computation descends directly from the classical logic-circuit diagrams of Boolean circuit theory, adapted to the reversible, unitary setting once physicists began asking how quantum mechanics could compute.

Every major quantum software development kit — Qiskit, Cirq, Q#, PennyLane — renders and edits programs as circuit diagrams, because the diagram is the natural user interface for the Quantum Circuit Model: dragging a gate box onto a wire is inserting a matrix factor into the product. Hardware compilers ("transpilers") take a high-level circuit diagram and rewrite it into an equivalent diagram using only gates a specific quantum processor natively supports (for example, decomposing an abstract SWAP into the three-CNOT form, or decomposing a Toffoli into two-qubit gates plus single-qubit rotations), directly using the reading/building procedures described here. Research papers proposing new algorithms — from Grover's search to quantum error-correcting codes — communicate their construction almost entirely through annotated circuit diagrams, making diagram literacy a prerequisite for reading the primary literature. Quantum hardware benchmarking reports width, depth, and gate count (exactly the three metrics above) as the standard way to compare how "expensive" a given circuit is to run on noisy near-term devices. And every course or textbook that introduces entanglement, teleportation, or superdense coding begins with the Bell-state circuit built in this article, making it the single most reused diagram in the entire subject.

Ask the tutor: How do I decompose a controlled-phase gate or a Toffoli into a diagram using only single-qubit gates and CNOTs?