Inference Serving Systems
Inference serving systems are the software and hardware infrastructure responsible for deploying trained machine learning models and responding to prediction requests at production scale, managing latency, throughput, and resource utilization simultaneously. They matter because a model that cannot serve millions of requests per second with sub-100ms latency has no real-world value, regardless of its validation accuracy. The counterintuitive fact: the engineering complexity of inference serving often exceeds that of training — a model trains once, but serves billions of times under wildly unpredictable load.
Training a model and serving a model are fundamentally different problems. Training optimizes for final accuracy over many hours on a fixed dataset; serving optimizes for latency, throughput, and cost per query under variable, bursty, real-world traffic — often with contradictory constraints. The "aha moment" is realizing that every design decision in a serving system — batching, caching, quantization, scheduling — is a deliberate trade-off on the latency–throughput–cost trilemma, and there is no universally correct answer, only the right answer for your specific service-level objective (SLO).
How It Works
The Latency–Throughput Trade-off
At the heart of every inference server is a scheduling loop that decides when to execute a batch of requests. Let be the batch size, be the time to run one forward pass on a batch of size , and be the time a single request spends waiting to be included in a batch.
Explanation: Throughput is the number of requests completed per unit time; increasing batch size amortizes fixed overhead but increases for early arrivals.
- — batch size (number of concurrent requests processed together)
- — GPU kernel execution time, which grows sub-linearly with due to parallelism
- — queuing latency before a request is dispatched
For transformer models, is dominated by matrix multiplications. Given weight matrix and an input batch :
Explanation: Doubling batch size doubles the FLOPs linearly, but memory-bandwidth-bound operations amortize the weight-load cost across more requests, so wall-clock time grows much slower than linearly.
- — output activations
- FLOPs — floating-point operations; the factor of 2 accounts for multiply-accumulate (MAC) operations
KV-Cache and Memory Footprint
Autoregressive transformer serving introduces a unique cost: the key-value cache. During generation of a sequence of length with attention heads, head dimension , and layers, the KV-cache memory requirement is:
Explanation: The factor of 2 accounts for both keys and values; this grows linearly with sequence length and batch size , quickly exhausting GPU VRAM for long contexts.
- — number of transformer layers
- — number of attention heads
- — per-head dimension
- — current sequence length (grows token by token during generation)
- — 2 bytes for FP16, 1 byte for INT8
For a typical 70B parameter model (e.g., Llama-3-70B) with , , , serving a batch of requests with tokens in FP16:
Explanation: This single calculation reveals why KV-cache management — through techniques like PagedAttention — is the dominant memory challenge in LLM serving, often exceeding the model weights themselves.
Goodput and SLO Attainment
A production serving system is judged not by raw throughput but by goodput — the fraction of requests completed within the latency SLO:
Explanation: A system that processes 10,000 requests/second but violates the 200ms SLO for 30% of them delivers only 7,000 useful completions per second — the SLO attainment rate is the true production metric.
- — empirical fraction of requests meeting the latency budget
- This motivates tail-latency optimization, not just mean-latency optimization
Ion Stoica is a professor at UC Berkeley and co-founder of Anyscale and Databricks, with foundational contributions to distributed systems including Apache Spark. He led the Berkeley Sky Computing Lab team that developed vLLM and the PagedAttention algorithm, which manages KV-cache memory using virtual memory paging principles borrowed from operating systems, enabling 24× higher throughput than naive implementations. Remarkably, his most influential AI systems work came after he was already famous in the distributed-systems community — a rare cross-domain leap that reshaped LLM deployment.
Woosuk Kwon is a PhD student at UC Berkeley (now faculty at University of Washington) who, as the lead author of the vLLM paper (2023), designed the PagedAttention algorithm that revolutionized LLM serving. PagedAttention treats the KV-cache as a set of non-contiguous fixed-size memory blocks — analogous to virtual memory pages — eliminating fragmentation and enabling near-zero memory waste during dynamic generation. Kwon was completing his PhD when vLLM became one of the fastest-adopted open-source inference systems in history, reaching millions of daily users within months of release.
Intuition
Think of an inference server as a restaurant kitchen, not an assembly line. In static batching (assembly-line thinking), the kitchen waits until exactly four orders arrive, cooks them all together, then plates everything simultaneously — even if one dish was done ten minutes ago. The early diners sit waiting while their food gets cold, and new customers can't even order until the batch finishes. Continuous batching is the smart kitchen: the moment a burner frees up, a new dish goes on it, regardless of what else is cooking. Requests come and go at token-generation frequency, not at request boundary frequency. The KV-cache is your kitchen's mise en place — pre-chopped ingredients (pre-computed attention keys and values) that make each new step fast. But the mise en place takes up counter space, and when the counter is full, you have to decide which prep to throw away or temporarily store elsewhere (offloading to CPU RAM). The scheduler is the head chef, constantly deciding who gets a burner, who waits, and which prep to keep on the counter — with the goal of keeping every burner running at 100% without burning anyone's order.