Rectifiers

Every charger, adapter and power supply on your desk starts with the same problem: the wall socket delivers alternating current (AC), reversing direction fifty times a second, but the circuits inside — batteries charging, chips computing — need direct current (DC), flowing one way only. The p-n junction diode's one-way-street property is the fix: because it conducts only when forward biased and blocks when reverse biased, wiring one (or two) into the AC path lets current through for part of the cycle and shuts it off for the rest. That circuit is a rectifier, the first stage inside almost every DC power supply. This article covers the two rectifier circuits prescribed for this syllabus — the single-diode half-wave rectifier and the two-diode, centre-tapped-transformer full-wave rectifier — with the role of every component, the peak-voltage relation that governs both, and why the 4-diode bridge rectifier, common in other textbooks, is explicitly excluded here.

The core insight

A diode conducts only when forward biased, so placing one across an AC source and a load resistor passes current for the forward half-cycle and blocks it for the reverse half-cycle, converting AC into pulsating DC — one pulse per cycle with a single diode (half-wave), two pulses per cycle with two diodes on a centre-tapped transformer (full-wave).

The core idea

Why a diode rectifies. A diode's resistance is low in forward bias and effectively infinite in reverse bias. Feed it a sinusoidal input and this asymmetry is the entire trick: whichever half-cycle happens to forward-bias the diode passes through to the load, and the other half is thrown away. Nothing in the diode needs to "know" it is rectifying — it is simply obeying its own current-voltage behaviour every instant.

Half-wave rectifier. A step-down transformer feeds a single diode in series with a load resistor RLR_L. On the positive half-cycle the diode is forward biased and conducts, so the output follows the input; on the negative half-cycle it is reverse biased and blocks, so the output is zero. One pulse of output per input cycle, with the other half of every cycle wasted — poor efficiency, large ripple.

Full-wave rectifier (centre-tapped). A transformer with a centre-tapped secondary feeds two diodes D1D_1, D2D_2 joined at a common output node, with RLR_L between that node and the centre tap. On one half-cycle the top half of the winding is positive relative to the tap, so D1D_1 conducts while D2D_2 blocks; on the other half-cycle the polarities swap and D2D_2 conducts while D1D_1 blocks. Because exactly one diode is always conducting, current flows through RLR_L in the same direction throughout — two pulses per input cycle, smoother and more efficient than half-wave.

Component roles. The transformer steps mains AC down to a safe level (and, for full-wave, supplies the two out-of-phase secondary voltages through its centre tap); each diode does the actual rectifying by conducting on its assigned half-cycle only; RLR_L is where the pulsating DC output is delivered and measured. A smoothing capacitor is often added after RLR_L to flatten the ripple, but filter design is beyond this syllabus. For either circuit, the instantaneous output across RLR_L follows the input exactly whenever the conducting diode is forward biased, and drops to zero whenever it is not:

Vout(t)={Vin(t),Vin(t)>0 (diode forward biased)0,Vin(t)≤0 (diode reverse biased)V_{out}(t) = \begin{cases} V_{in}(t), & V_{in}(t) > 0 \ \text{(diode forward biased)} \\ 0, & V_{in}(t) \le 0 \ \text{(diode reverse biased)} \end{cases}

where: Vin(t)V_{in}(t) is the instantaneous AC input reaching the diode, Vout(t)V_{out}(t) is the instantaneous voltage across RLR_L, and the diode is treated as ideal (zero forward drop, infinite reverse resistance) unless stated otherwise. For the full-wave circuit this same rule applies separately to each diode and each half of the secondary, with the two outputs stacking so the load never sees zero for more than an instant.

Figure
Input sine wave alongside the half wave rectifier output showing only positive lobes and the full wave rectifier output showing both lobes flipped upward
From AC input to rectified output — half wave versus full wave AC input Half wave output — one pulse per cycle Full wave output — two pulses per cycle, always positive Half wave keeps only the forward biased lobes; full wave routes both lobes the same way through the load, doubling the pulse rate.
Derivation APeak output voltage of a half-wave rectifier, ideal versus real diode

The goal is to derive, from Kirchhoff's voltage law and the diode's own forward-bias state, why the peak output voltage across RLR_L equals the peak input voltage for an ideal diode, and why a real silicon diode's forward barrier potential shaves a fixed amount off that peak — a distinction worth knowing precisely rather than blurred, since exam questions can quote either an ideal or a real diode.

Step 1. Write Kirchhoff's voltage law around the single loop of the half-wave circuit: the AC source, the diode, and RLR_L are all in series, so at any instant Vin(t)=VD+I(t) RLV_{in}(t) = V_D + I(t)\,R_L, where VDV_D is the voltage dropped across the conducting diode and I(t)I(t) is the loop current.

Step 2. For an ideal diode in forward bias, VD=0V_D = 0 by definition (zero forward resistance, no drop). The loop equation collapses to Vin(t)=I(t) RLV_{in}(t) = I(t)\,R_L, so the entire input appears across the load: Vout(t)=I(t) RL=Vin(t)V_{out}(t) = I(t)\,R_L = V_{in}(t). At the crest of the input cycle this gives Vout,peak=V0V_{out,peak} = V_0, exactly the result used in the worked example below.

Step 3. For a real silicon diode, forward conduction only begins once Vin(t)V_{in}(t) exceeds a barrier potential Vγ≈0.7 VV_\gamma \approx 0.7\ \text{V}, and beyond that point the diode drops approximately this fixed VγV_\gamma regardless of current. The loop equation becomes Vin(t)=Vγ+I(t) RLV_{in}(t) = V_\gamma + I(t)\,R_L, so Vout(t)=Vin(t)−VγV_{out}(t) = V_{in}(t) - V_\gamma whenever Vin(t)>VγV_{in}(t) > V_\gamma. At the input crest, Vout,peak=V0−VγV_{out,peak} = V_0 - V_\gamma — slightly less than the ideal value, and zero output whenever Vin(t)V_{in}(t) stays below VγV_\gamma near each zero-crossing.

Step 4. For the reverse half-cycle, the diode carries (ideally) no current, so I(t)=0I(t) = 0 and Vout(t)=0V_{out}(t) = 0; the entire input instead appears across the (very large) reverse resistance of the diode itself. The maximum reverse voltage the diode must withstand without breaking down is the peak inverse voltage, equal to V0V_0 for the half-wave circuit — a rating diodes are chosen to exceed.

Worked example

Question: A half-wave rectifier is fed a sinusoidal AC input of peak voltage V0=10 VV_0 = 10\ \text{V}, in series with a 1 kΩ1\,\text{k}\Omega load resistor. Find the peak output voltage (a) for an ideal diode and (b) for a real silicon diode with barrier potential Vγ=0.7 VV_\gamma = 0.7\ \text{V}. (c) State the peak inverse voltage the diode must withstand.

Step 1. Ideal diode, forward half-cycle: from Step 2 of the derivation, VD=0V_D = 0, so Vout,peak=V0=10 VV_{out,peak} = V_0 = 10\ \text{V}.

Step 2. Real diode, forward half-cycle: from Step 3 of the derivation, Vout,peak=V0−Vγ=10−0.7=9.3 VV_{out,peak} = V_0 - V_\gamma = 10 - 0.7 = 9.3\ \text{V}. The output tracks the input shape but rides 0.7 V0.7\ \text{V} lower, and the diode stays off while Vin(t)<0.7 VV_{in}(t) < 0.7\ \text{V} near each crossing — a small dead zone the ideal model ignores.

Step 3. Reverse half-cycle, either model: the diode blocks, so Vout=0 VV_{out} = 0\ \text{V}, and it must withstand the full reverse swing without breaking down. The peak inverse voltage rating needed is PIV=V0=10 V\text{PIV} = V_0 = 10\ \text{V}.

Conclusion: the ideal-diode peak output is 10 V, the real-diode peak output is 9.3 V, and the diode must be rated to withstand at least 10 V in reverse.

Common traps

  • Drawing or describing a 4-diode bridge rectifier — explicitly out of scope for this syllabus; only the single-diode half-wave and two-diode centre-tapped full-wave circuits are prescribed.
  • Forgetting that in the full-wave circuit only one diode conducts at a time, never both simultaneously.
  • Treating rectifier output as smooth, ripple-free DC — without a smoothing filter it is still pulsating: one direction only, but the magnitude varies with time.
  • Using the ideal-diode formula (Vout,peak=V0V_{out,peak}=V_0) when a real diode's barrier potential VγV_\gamma is explicitly given in the question — the peak drops to V0−VγV_0-V_\gamma.
  • Mixing up pulses per cycle — half-wave gives one output pulse per input cycle; full-wave gives two.

Ask the tutor: if you want to see how a smoothing capacitor reshapes the output, or work through ripple factor and average DC voltage numerically, ask the AI tutor to walk through a few more rectifier problems.

Why does the full-wave rectifier need a centre-tapped transformer instead of just two diodes on a normal transformer?

The centre tap supplies the reference point that RLR_L connects to, and it splits the secondary into two windings that are always equal in magnitude but opposite in phase — when the top half is positive relative to the tap, the bottom half is negative by exactly the same amount, and vice versa. That guaranteed opposite-phase pair is what lets D1D_1 and D2D_2 take turns conducting on alternate half-cycles while always driving current through RLR_L in the same direction. Without the centre tap there would be no shared reference node for the two diodes to route current back to, and the "two pulses in the same direction" behaviour would not work.

Is the smoothing capacitor part of this syllabus, and why is a bare rectifier output not already smooth DC?

The smoothing capacitor and filter-circuit design are beyond this syllabus — you only need to know a capacitor is often added after RLR_L to reduce ripple, not calculate its effect. A bare rectifier output is not smooth because the diode's conduction is on-off: current flows only while a diode is forward biased, so the voltage across RLR_L rises and falls (or, for half-wave, rises and falls to zero) every half-cycle. It is DC in the sense that it never reverses direction, but its magnitude keeps pulsing — genuinely smooth DC needs a filter stage after the rectifier.

Why is a real diode's forward voltage drop around 0.7 V specifically, and does it change with load?

The 0.7 V figure is the approximate barrier (or "cut-in") potential of a silicon p-n junction — the voltage needed to overcome the built-in potential barrier at the junction before appreciable forward current flows, a property of silicon itself rather than of the circuit around it. Once conducting, the drop stays close to this value across a wide range of forward currents, which is why it is treated as a fixed constant (Vγ≈0.7 VV_\gamma \approx 0.7\ \text{V} for silicon) in circuit calculations rather than something that needs recalculating for every load resistor. Germanium diodes, by contrast, have a lower barrier potential of about 0.3 V, though silicon is the standard assumption unless a question states otherwise.

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