Clocks and Timing

A clock signal is a periodic waveform, typically a square wave, that alternates between logic 0 and logic 1 with a fixed clock period T (equivalently, clock frequency f = 1/T). In an edge-triggered synchronous design, every flip-flop in the circuit shares this same clock signal and updates its stored state on the same type of edge — commonly the rising edge. Between clock edges, combinational logic computes new values from the current flip-flop outputs; at the next edge, those new values are captured into the flip-flops, becoming the new state. This discipline — state changes only at clock edges, combinational logic settling in between — is what makes a large digital system behave as a predictable, composable finite state machine rather than an unmanageable tangle of feedback loops. Making this work requires respecting the physical reality that no signal changes instantaneously. Three delay parameters govern correctness:

• Propagation delay from clock to output, t_pcq — the time after a clock edge until a flip-flop's output Q becomes valid and stable.
• Combinational propagation delay, t_pd — the time for a signal to pass through the logic gates between one flip-flop's output and the next flip-flop's input.
• Setup time, t_su — the minimum time before the next clock edge that a flip-flop's data input D must be stable, so the flip-flop can reliably capture it.
• Hold time, t_h — the minimum time after the clock edge that D must remain stable, so the capture is not corrupted by a new value arriving too soon.

Setup and hold time together define an aperture window around the clock edge — a narrow interval during which the D input must not change, on pain of the flip-flop entering a metastable state (an unpredictable, sometimes intermediate, voltage that violates the digital abstraction entirely). The entire art of timing analysis is ensuring every signal path in the circuit respects this aperture, for every flip-flop, on every clock edge, under worst-case conditions.

Timing analysis treats the circuit as a graph: flip-flops are nodes, and combinational logic paths between them are edges weighted by propagation delay. The analysis walks every register-to-register path — from one flip-flop's clock edge, through combinational logic, to the next flip-flop's data input — and checks two independent inequalities.

Setup analysis asks: does the signal arrive early enough? Starting at time 0 (the launching clock edge), the launching flip-flop's output becomes valid after t_pcq. The signal then propagates through combinational logic, taking up to t_pd(max) in the worst case (longest path, slowest gates, worst temperature/voltage corner). It must arrive at the capturing flip-flop's D input and be stable at least t_su before the next clock edge, which occurs at time T. This gives the fundamental setup-time constraint: ``` T ≥ t_pcq + t_pd(max) + t_su ``` Solving for the maximum clock frequency: ``` f_max = 1 / (t_pcq + t_pd(max) + t_su) ```

Hold analysis asks a different question entirely: does the signal arrive too early, before the current capture is even finished? The capturing flip-flop needs D to remain stable for t_h after the clock edge at time 0. If the combinational path is extremely short (t_pd(min), the fastest possible path — think a single buffer or a direct wire), the new data value can race through and reach D before the hold aperture closes. This gives the hold-time constraint, which is completely independent of the clock period: ``` t_pcq + t_pd(min) ≥ t_h ``` Notice T does not appear in the hold-time inequality. This is the source of a critical asymmetry: setup violations can be fixed by slowing the clock down; hold violations cannot. A hold violation is a structural flaw — the path is simply too fast relative to the flip-flop's hold requirement — and must be fixed by adding deliberate delay (buffers) into the path, not by changing frequency. The full timing-analysis algorithm, run by every static timing analysis (STA) tool in industry, generalizes this to every path in the circuit: ``` function static_timing_analysis(circuit, T): violations = [] for each register-to-register path p in circuit: launch_ff = source flip-flop of p capture_ff = destination flip-flop of p t_pd_max = worst_case_propagation_delay(p) t_pd_min = best_case_propagation_delay(p)

# Setup check: does data arrive in time for the NEXT edge? arrival_time = launch_ff.t_pcq + t_pd_max required_time = T - capture_ff.t_su slack_setup = required_time - arrival_time if slack_setup < 0: violations.append(("SETUP", p, slack_setup))

# Hold check: does data arrive too early, corrupting THIS edge? earliest_arrival = launch_ff.t_pcq + t_pd_min slack_hold = earliest_arrival - capture_ff.t_h if slack_hold < 0: violations.append(("HOLD", p, slack_hold)) return violations function max_clock_frequency(circuit): worst_setup_sum = max over all paths p of (launch_ff.t_pcq + worst_case_propagation_delay(p) + capture_ff.t_su) return 1 / worst_setup_sum ``` Real designs add two more terms to account for imperfect clock distribution:

• Clock skew (t_skew) — the difference in arrival time of the clock edge at the launching versus the capturing flip-flop, caused by unequal wire lengths in the clock tree.
• Clock jitter (t_jitter) — cycle-to-cycle variation in the clock edge's actual timing, caused by noise in the clock generation circuit (e.g., a PLL).

With skew and jitter, the setup inequality becomes: ``` T ≥ t_pcq + t_pd(max) + t_su + t_skew + t_jitter ``` and the hold inequality becomes: ``` t_pcq + t_pd(min) ≥ t_h + t_skew + t_jitter ``` Positive skew (capturing clock arrives later than launching clock) helps setup timing but hurts hold timing, and vice versa — another reason hold violations are treated as structural, not tunable-by-frequency, problems.

Complexity of static timing analysis. Model the circuit's register-to-register structure as a directed acyclic graph restricted to combinational logic, with N flip-flops and E wires/gate connections forming the combinational paths between them. Computing the worst-case (longest) delay from every launching flip-flop to every capturing flip-flop is a longest-path problem on a DAG, solvable by a single topological-order dynamic-programming pass: ``` delay[node] = max over all predecessors p of (delay[p] + gate_delay(p, node)) ``` This runs in O(V + E) time, where V is the number of gates/nets and E is the number of connections — linear in circuit size, because a DAG longest-path computation requires only one topological traversal (unlike longest path in a general graph, which is NP-hard; acyclicity is what saves us, and it holds because combinational logic between clocked elements is, by construction of a synchronous design, feedback-free). The same DAG shortest-path computation (replacing max with min) yields t_pd(min) for hold-time checking in the same O(V + E) time. Real STA tools repeat this for every clock domain and every process/voltage/temperature corner, so total runtime scales with (number of corners) × O(V + E), still linear in circuit size per corner — which is why STA scales to chips with billions of transistors, whereas exhaustive simulation of all input combinations would be exponential.

Correctness argument for the setup inequality. Consider any register-to-register path. The launching flip-flop's Q output is guaranteed stable no earlier than t_pcq after its clock edge (by the flip-flop's datasheet specification). The combinational logic adds at most t_pd(max) additional delay in the worst case over all input combinations and process variation — this is precisely the definition of worst-case propagation delay, and correctness requires designers to use the true worst case, not a typical case, since a timing analyzer that underestimates delay gives no guarantee at all. Therefore the data at the capturing flip-flop's D input is guaranteed stable by time t_pcq + t_pd(max) after the launch edge. For the capture to succeed, this must occur at least t_su before the capturing edge, which arrives at time T. Rearranging t_pcq + t_pd(max) ≤ T − t_su gives exactly the setup inequality. This is not a heuristic — it is a direct consequence of the definitions of t_pcq, t_pd, and t_su as worst-case/required guarantees, so if the inequality holds for every path, every flip-flop is guaranteed to capture correct data on every cycle, for every possible input sequence and every allowed process/voltage/temperature condition. This constitutes an inductive invariant: if the state is correct at the start of a cycle, the inequality guarantees the state is correct at the start of the next cycle, so by induction the circuit is correct for all cycles.

Correctness argument for the hold inequality. Symmetric reasoning with best-case (minimum) delay: the fastest the new data can possibly reach D is t_pcq + t_pd(min) after the launch edge, which is the same clock edge that is currently being used to capture the previous value at the capturing flip-flop (since hold time is measured relative to the same edge, not the next one). If this earliest arrival is sooner than t_h after that edge, the new value corrupts the capture that is still in progress — the capturing flip-flop needs its input undisturbed for t_h past the edge it is using. Hence t_pcq + t_pd(min) ≥ t_h is required.

Tradeoffs. Setup violations are a global frequency problem — fixed by increasing T (lowering clock frequency) uniformly, or by re-timing/pipelining to shorten the worst path. Hold violations are a local structural problem, fixed only by inserting buffer delay onto specific fast paths; they persist at any clock frequency, including very slow ones, since the hold inequality never involves T. This asymmetry is why hold violations discovered late in a chip design are far more feared than setup violations: a setup miss can sometimes be patched by "binning" a chip to run slower, but a hold violation makes a chip fundamentally broken at every speed and typically requires a costly redesign (a new mask set).

Consider a synchronous circuit with the following characteristics, values in a plausible range for a modern standard-cell flip-flop:

Step 1 — compute the minimum clock period from the setup inequality: ``` T ≥ t_pcq + t_pd(max) + t_su + t_skew + t_jitter T ≥ 80 + 620 + 50 + 10 + 5 T ≥ 765 ps ```

Step 2 — compute the maximum clock frequency: ``` f_max = 1 / T = 1 / 765 ps ≈ 1.307 GHz ``` So this circuit can run no faster than roughly 1.31 GHz; any faster and the critical path's data would arrive after the setup aperture opens, risking a metastable capture.

Step 3 — check the hold inequality on the fastest path (independent of clock frequency): ``` t_pcq + t_pd(min) ≥ t_h + t_skew + t_jitter 80 + 15 ≥ 40 + 10 + 5 95 ≥ 55 ✓ satisfied, with 40 ps of hold slack ``` The hold check passes with margin, so this design is safe at 1.31 GHz and would remain safe even if we clocked it at 1 MHz — hold time truly does not care about T.

Step 4 — a cautionary variant. Suppose an aggressive synthesis tool "optimizes" a nearby short path down to t_pd(min) = 2 ps (perhaps by removing a buffer it judged unnecessary for area). Recheck hold: ``` 80 + 2 ≥ 40 + 10 + 5 82 ≥ 55 ✓ still satisfied ``` Still fine here — but suppose instead the flip-flop's t_h were 70 ps (a slower, higher-threshold cell) and skew were larger, say 20 ps: ``` 80 + 2 ≥ 70 + 20 + 5 82 ≥ 95 ✗ VIOLATED ``` This circuit now fails hold timing by 13 ps. Crucially, no adjustment to the clock period fixes this — the fix is to insert roughly 13–15 ps of extra buffer delay into that specific short path, increasing t_pd(min) until the inequality holds again. This is exactly the kind of fix physical-design engineers apply during "hold-fixing" iterations late in chip layout.

The formalization of synchronous timing analysis grew out of the broader history of sequential circuit theory, digital computer design, and the discipline of VLSI timing verification that emerged as chips grew too large for exhaustive simulation.

Timing analysis governs every synchronous digital system in production. Microprocessor design teams run static timing analysis on billions of register-to-register paths to determine the maximum safe clock frequency before a chip ever reaches silicon — the number printed on a CPU's box (e.g., "3.5 GHz") is fundamentally a setup-time calculation like the one above, taken across the slowest path on the chip under worst-case conditions. Field-Programmable Gate Arrays (FPGAs) run timing analysis after every synthesis and place-and-route pass, reporting "timing closure" or a list of failing paths that a designer must fix by re-pipelining or floorplanning. High-speed memory interfaces (DDR, PCIe, USB) depend on careful hold-time budgeting between chips on a circuit board, where clock skew across board traces becomes a dominant term. Automotive and aerospace electronics apply the same setup/hold discipline with extra safety margin because a metastability event in a flight-control system is unacceptable. Every course and career built on Registers and Register Files and pipelined Finite State Machines ultimately rests on this same pair of inequalities — the same reasoning determines whether a five-stage CPU pipeline can be clocked at 2 GHz or must be redesigned with shorter stages.

Ask the tutor: How does clock skew across multiple clock domains complicate timing analysis when signals cross from one domain to another?