Latches and Flip-Flops

A latch is a bistable circuit: a circuit with exactly two stable output configurations, each of which persists forever in the absence of a new input, because the output is wired back as an input to itself. This feedback is the entire trick. Two NOR gates, or two NAND gates, cross-coupled so that each gate's output feeds the other gate's input, have two self-consistent equilibrium states (Q=0,Q̄=1) and (Q=1,Q̄=0). Which one the circuit sits in depends on its history — that history-dependence is memory. A latch is called level-sensitive (or transparent) because whenever its enable/clock input is asserted (at the "1" level, say), its output tracks its data input immediately, gate-delay only; it is not waiting for any special moment. A flip-flop is a memory element whose output can change only at a controlled instant, usually the rising or falling edge of a clock signal, rather than throughout an entire clock level. This is called edge-triggering. The distinction between level-sensitive latches and edge-triggered flip-flops is the single most important vocabulary distinction in sequential logic: a latch is "open" (transparent) for a whole half-cycle, during which glitches or races can propagate straight through it, while a flip-flop is open for only an instant, decoupling its output change from any lingering transients on its input. The three circuits in this article's scope form a strict progression. The SR latch (Set-Reset) is the primitive cross-coupled circuit, simplest to build and reason about but flawed: one input combination is "forbidden" because it makes both outputs equal and leaves the next state ambiguous. The D latch (Data/Delay latch) wraps an SR latch (or is built directly from a multiplexer-like gate structure) so that only one data line D and one enable line C are exposed; the forbidden state is architecturally impossible because S and R can never both be asserted. The edge-triggered D flip-flop, most commonly realized as a master-slave pair of D latches driven by complementary clock phases, converts the D latch's whole-half-cycle transparency into a single-instant sample-and-hold, producing the element every synchronous digital system is built from.

The SR latch. Build it from two cross-coupled NOR gates. Gate 1 computes Q = NOR(R, Q̄); gate 2 computes Q̄ = NOR(S, Q). The truth table, checked case by case:

When S=1, R=0, gate 2 forces Q̄=0 regardless of its other input, and gate 1 then sees R=0, Q̄=0, giving Q = NOR(0,0) = 1 — consistent. Symmetric reasoning gives the Reset row. When S=R=0, whichever value Q currently holds is self-sustaining: if Q=1, Q̄=NOR(0,1)=0, and Q=NOR(0,0)=1, consistent; if Q=0, Q̄=NOR(0,0)=1, and Q=NOR(0,1)=0, also consistent — both states are stable, which is exactly the bistability that gives us memory. When S=R=1, both outputs are forced to 0, violating the invariant Q=NOT(Q̄) that defines a well-formed latch state; the moment S and R are released, whichever gate reacts faster wins unpredictably — a race condition. This is why S=R=1 is forbidden in normal operation.

The D latch. Take an SR latch and add a transparent-gating layer with a single enable input C (clock/control): feed S = D AND C, and R = (NOT D) AND C. When C=0, S=R=0 regardless of D, so the latch holds its last value. When C=1, S and R are complements of each other, so S=R=1 is structurally impossible — the forbidden state is eliminated by construction. While C=1, Q follows D immediately (transparency).

The edge-triggered D flip-flop (master-slave). Chain two D latches: a master latch gated by clock CLK, and a slave latch gated by the inverted clock NOT CLK. While CLK=0, the master is transparent (tracks D) and the slave is opaque (holds its old value, isolating the output). While CLK=1, the master becomes opaque (freezing whatever value D held at the instant CLK rose) and the slave becomes transparent, copying that frozen value to the output Q. Because the master closes at the exact instant the slave opens, the only moment the external input D affects the external output Q is the rising edge of CLK — everywhere else, one of the two latches is opaque and blocks propagation. This is what "edge-triggered" means operationally: sensitivity to D is compressed into an instant, even though internally the circuit is built from two ordinary level-sensitive latches. ```pseudocode // SR latch — state held in Q, Q_bar; feedback defines next state function SR_LATCH_STEP(S, R, Q, Q_bar): if S == 1 and R == 1: error("forbidden input combination") // both outputs would go low Q_next = NOR(R, Q_bar) Q_bar_next = NOR(S, Q) return (Q_next, Q_bar_next) // D latch — level sensitive, transparent while C == 1 function D_LATCH_STEP(D, C, Q): if C == 1: Q = D // transparent: output follows input instantly // else: C == 0, Q holds its previous value (no assignment) return Q // Edge-triggered D flip-flop, master-slave construction // Internally two D latches; externally samples D only at CLK rising edge function DFF_STEP(D, CLK, master_Q, slave_Q): master_C = NOT(CLK) slave_C = CLK master_Q = D_LATCH_STEP(D, master_C, master_Q) // opaque while CLK=1 slave_Q = D_LATCH_STEP(master_Q, slave_C, slave_Q) // opaque while CLK=0 Q = slave_Q return (Q, master_Q, slave_Q) ```

Time complexity. Every operation on a latch or flip-flop — set, reset, hold, or clocked update — takes O(1) time: a fixed, small number of gate propagation delays independent of any input size, because there is no notion of "problem size" for a single bit. The relevant real-world timing quantities are not asymptotic but physical: propagation delay (t_pd, gate-to-output delay), setup time (t_su, how long D must be stable before the clock edge), and hold time (t_h, how long D must remain stable after the edge). A flip-flop is used correctly only if D is stable throughout the window [edge − t_su, edge + t_h]; this is a timing constraint, not a complexity bound, but it plays the same role in correctness that loop invariants play in iterative algorithms.

Space complexity. Storing one bit costs O(1) space — a constant number of gates (2 cross-coupled gates for an SR latch, roughly 4–6 gates for a D latch, and about double that, ~8–12 gates, for a master-slave D flip-flop). An n-bit register built from n flip-flops costs Θ(n) gates and Θ(n) area, which is the expected linear scaling and is why Registers and Register Files are described as arrays of this same one-bit primitive.

Correctness argument — SR latch. The claim is that the cross-coupled NOR pair has exactly two stable fixed points under S=R=0, and that S=1,R=0 (respectively S=0,R=1) drives the circuit to the Q=1 (respectively Q=0) fixed point regardless of starting state. Proof sketch: treat (Q, Q̄) as a state and check self-consistency of the defining equations Q = NOR(R,Q̄), Q̄ = NOR(S,Q) under each input. For S=0,R=0: Q=1,Q̄=0 satisfies Q=NOR(0,0)=1 ✓ and Q̄=NOR(0,1)=0 ✓; likewise Q=0,Q̄=1 is also self-consistent — two fixed points confirmed, i.e., bistability, the defining property of memory. For S=1,R=0: Q̄ = NOR(0,Q) is forced toward 0 once we substitute the target Q=1 (Q̄=NOR(0,1)=0), and then Q=NOR(0,0)=1, a self-reinforcing loop that converges to Q=1 from either starting state — this is the "Set" behavior working correctly. The forbidden case S=R=1 breaks the invariant Q=NOT(Q̄) (both go to 0 simultaneously), so the two-fixed-point argument does not apply, and the state reached when S and R are simultaneously released depends on gate-delay mismatches — an unavoidable race, which is exactly why the input combination is disallowed by contract rather than fixed by circuitry.

Correctness argument — D latch. Because S = D∧C and R = D̄∧C are complementary whenever C=1 (one of D, D̄ is always 0, so S and R cannot both be 1), the forbidden SR state is provably unreachable — not merely avoided by careful use, but structurally excluded. This is a stronger correctness guarantee: a proof by construction rather than a usage discipline. When C=0, S=R=0 regardless of D, which by the SR latch's own correctness argument means Q holds its last value — giving the desired "opaque when disabled" behavior.

Correctness argument — edge-triggered flip-flop. The master-slave design's correctness rests on an invariant: at every instant, at most one of the two latches is transparent. Master is transparent exactly when CLK=0; slave is transparent exactly when CLK=1; these conditions are mutually exclusive (ignoring the zero-width instant of an idealized transition), so there is never a moment when D has a direct combinational path all the way to Q. Consequently Q can change only during the CLK transition itself, when control passes from master to slave — this is the formal justification for calling the device "edge-triggered" despite being built from two purely level-sensitive latches. The tradeoff is a doubling of gate count and an added full latch-delay of propagation time (data must pass through both master and slave), compared to a single (unsafe, transparent) D latch — the classic time/robustness tradeoff of adding a second stage to gain edge sensitivity.

Trace a master-slave D flip-flop through a sequence of (D, CLK) inputs, assuming instantaneous gate response for clarity and starting from Q=0, master_Q=0.

The critical row is step 3: D changes from 1 to 0 while CLK is already high (mid-level, not at an edge). Because the slave is transparent during CLK=1 and mirrors the master, one might worry Q would glitch — but the master is opaque during CLK=1 (it closed at the edge in step 2), so the new D=0 has no path to the master's output, hence none to Q. Q remains a stable 1 throughout the entire CLK=1 phase, changing only at the next rising edge (step 6), which correctly demonstrates edge-triggered behavior: input changes between edges are invisible to the output, exactly the property a plain, single-stage D latch would fail to provide (a D latch would have let Q glitch down to 0 in step 3, because D latches stay transparent for the whole enable level).

The cross-coupled bistable circuit predates the transistor: it was first realized with vacuum tubes as the Eccles-Jordan trigger circuit, the ancestor of every flip-flop built since, including the ones inside every modern CPU register.

Every synchronous digital system — from a simple 8-bit microcontroller to a many-core server processor — is built as combinational logic interspersed with banks of edge-triggered D flip-flops. The program counter, register file entries, and pipeline latches separating fetch/decode/execute/memory/writeback stages in a pipelined CPU are all literal instances of the D flip-flop described here, chosen specifically for its edge-triggered (not level-sensitive) behavior so that pipeline stages do not race each other within a single clock cycle. SRAM cells used in CPU caches and register files are themselves small cross-coupled bistable circuits, direct descendants of the SR latch topology, optimized for transistor count rather than input-count flexibility. FPGA fabric provides a configurable D flip-flop at every logic cell, letting designers build arbitrary Finite State Machines whose entire notion of "current state" is stored across that layer of flip-flops. Serial interfaces and clock-domain-crossing logic use chains of flip-flops as synchronizers to manage the metastability risk discussed above. In short, this article's three circuits are the atomic storage unit beneath Registers and Register Files, the state memory beneath every hardware Finite State Machine, and the reason Clocks and Timing exists as a discipline: someone must guarantee that every flip-flop's setup and hold windows are respected on every single edge, every cycle, across an entire chip.

Ask the tutor: How does a master-slave D flip-flop's two-latch structure change if the design needs both a synchronous reset and an asynchronous clear input?